# 4-bit square root calculator
#
# This is the same digital circuit shown in Figure 6
# of Qian & Winfree (2014) but modified slightly to
# use the updated sCRN reaction set (110 reaction)
# of Clamons, Qian, Winfree (2020).
#
# Inputs are on the left, from top to bottom x1, x2, x3, x4.
# Outputs are on the bottom/right, from right to left y1, y2.
# The function computed is
#
#                             y2 y1 = floor( sqrt( x4 x3 x2 x1 ) )
#
# where the variables are the bits of a 4-bit input
# and a 2-bit output.

pixels_per_node    = 30
speedup_factor     = 100
debug              = True
max_duration       = 100
node_display      = color
# rng_seed           = 123123123

!START_TRANSITION_RULES
### WIRE RULES
### 2 rules
# Move
(1) 0 + B -> B + 0
(1) 1 + B -> B + 1


### OR GATE
### 14 rules
# Load
(1) 0 + BRx -> B + 0Rx
(1) 1 + BRx -> B + 1Rx
(1) 0 + BRy -> B + 0Ry
(1) 1 + BRy -> B + 1Ry
(1) 0Rx + BRz -> HRx + 0Rz
(1) 1Rx + BRz -> HRx + 1Rz
# Logic rules
(1) 0Ry + 0Rz -> HRy + 0Rk
(1) 0Ry + 1Rz -> HRy + 1Rk
(1) 1Ry + 0Rz -> HRy + 1Rk
(1) 1Ry + 1Rz -> HRy + 1Rk
# Unload
(1) 0Rk + B -> RRRz + 0
(1) 1Rk + B -> RRRz + 1
# Reset
(1) RRRz + HRx -> RRz + BRx
(1) RRz + HRy -> BRz + BRy


### XOR GATE
### 14 rules
# Load
(1) 0 + BXx -> B + 0Xx
(1) 1 + BXx -> B + 1Xx
(1) 0 + BXy -> B + 0Xy
(1) 1 + BXy -> B + 1Xy
(1) 0Xx + BXz -> HXx + 0Xz
(1) 1Xx + BXz -> HXx + 1Xz
# Logic rules
(1) 0Xy + 0Xz -> HXy + 0Xk
(1) 0Xy + 1Xz -> HXy + 1Xk
(1) 1Xy + 0Xz -> HXy + 1Xk
(1) 1Xy + 1Xz -> HXy + 0Xk
# Unload
(1) 0Xk + B -> RRXz + 0
(1) 1Xk + B -> RRXz + 1
# Reset
(1) RRXz + HXx -> RXz + BXx
(1) RXz + HXy -> BXz + BXy


### AND GATE
### 14 rules
# Load
(1) 0 + BAx -> B + 0Ax
(1) 1 + BAx -> B + 1Ax
(1) 0 + BAy -> B + 0Ay
(1) 1 + BAy -> B + 1Ay
(1) 0Ax + BAz -> HAx + 0Az
(1) 1Ax + BAz -> HAx + 1Az
# Logic rules
(1) 0Ay + 0Az -> HAy + 0Ak
(1) 0Ay + 1Az -> HAy + 0Ak
(1) 1Ay + 0Az -> HAy + 0Ak
(1) 1Ay + 1Az -> HAy + 1Ak
# Unload
(1) 0Ak + B -> RRAz + 0
(1) 1Ak + B -> RRAz + 1
# Reset
(1) RRAz + HAx -> RAz + BAx
(1) RAz + HAy -> BAz + BAy


### SYNC GATE
### 10 rules
# Load
(1) 0 + BSx -> B + 0Sx
(1) 1 + BSx -> B + 1Sx
(1) 0Sx + BSy -> BSx + 0Sy
(1) 1Sx + BSy -> BSx + 1Sy
# Synchronize
(1) 0Sy + 0Sy -> 0Sz + 0Sz
(1) 0Sy + 1Sy -> 0Sz + 1Sz
(1) 1Sy + 0Sy -> 1Sz + 0Sz
(1) 1Sy + 1Sy -> 1Sz + 1Sz
# Unload
(1) 0Sz + B -> BSy + 0
(1) 1Sz + B -> BSy + 1

### REPEATER GATE
### 6 rules
# Load
(1) 0 + BPx -> B + 0Px
(1) 1 + BPx -> B + 1Px
# Logic
(1) 0Px + BPy -> BPx + 0Pk
(1) 1Px + BPy -> BPx + 1Pk
# Unload
(1) 0Pk + B -> BPy + 0
(1) 1Pk + B -> BPy + 1

### NOT gate rules
### 6 rules
# Load
(1) 0 + BNx -> B + 0Nx
(1) 1 + BNx -> B + 1Nx
# Logic
(1) 0Nx + BNy -> BNx + 1Ny
(1) 1Nx + BNy -> BNx + 0Ny
# Unload
(1) 0Ny + B -> BNy + 0
(1) 1Ny + B -> BNy + 1


### 2-FAN-OUT
### 10 rules
# Load
(1) 0 + BF -> B + 0F
(1) 1 + BF -> B + 1F
# "Logic"
(1) 0F + BFx -> 0f + 0Fx
(1) 1F + BFx -> 1f + 1Fx
(1) 0f + BFy -> BF + 0Fy
(1) 1f + BFy -> BF + 1Fy
# Unload
(1) 0Fx + B -> BFx + 0
(1) 1Fx + B -> BFx + 1
(1) 0Fy + B -> BFy + 0
(1) 1Fy + B -> BFy + 1

### 3-FAN-OUT
### 14 rules
# Load
(1) 0 + BF3 -> B + 0FF
(1) 1 + BF3 -> B + 1FF
# "Logic"
(1) 0FF + BFx3 -> 0Ff + 0Fx3
(1) 1FF + BFx3 -> 1Ff + 1Fx3
(1) 0Ff + BFy3 -> 0ff + 0Fy3
(1) 1Ff + BFy3 -> 1ff + 1Fy3
(1) 0ff + BFz3 -> BF3 + 0Fz3
(1) 1ff + BFz3 -> BF3 + 1Fz3
# Unload
(1) 0Fx3 + B -> BFx3 + 0
(1) 1Fx3 + B -> BFx3 + 1
(1) 0Fy3 + B -> BFy3 + 0
(1) 1Fy3 + B -> BFy3 + 1
(1) 0Fz3 + B -> BFz3 + 0
(1) 1Fz3 + B -> BFz3 + 1

### WIRE CROSS
### 20 rules
# Load
(1) 0 + BCx -> B + 0Cx
(1) 1 + BCx -> B + 1Cx
(1) 0 + BCy -> B + 0Cy
(1) 1 + BCy -> B + 1Cy
# Signal push to center
(1) 0Cx + BC -> HCx + 0Cx
(1) 1Cx + BC -> HCx + 1Cx
(1) 0Cy + BC -> HCy + 0Cy
(1) 1Cy + BC -> HCy + 1Cy
# Signal push to output
(1) 0Cx + BCw -> BC + 0Cw
(1) 1Cx + BCw -> BC + 1Cw
(1) 0Cy + BCz -> BC + 0Cz
(1) 1Cy + BCz -> BC + 1Cz
# Unload
(1) 0Cw + B -> RCw + 0
(1) 1Cw + B -> RCw + 1
(1) 0Cz + B -> RCz + 0
(1) 1Cz + B -> RCz + 1
# Reset
(1) RCw + BC -> BCw + RCcw
(1) RCcw + HCx -> BC + BCx
(1) RCz + BC -> BCz + RCcz
(1) RCcz + HCy -> BC + BCy
!END_TRANSITION_RULES

!START_COLORMAP
# Color definitions for logic gates

# Color definitions for logic gates

### SIGNALS
{0 signal} 0, 0x, 0y, 0Xx, 0Xy, 0Xk, 0Xz, 0Rx, 0Ry, 0Rk, 0Rz, 0Ax 0Ay, 0Ax, 0Ay, 0Ak, 0Az, 0Nx, 0Ny, 0f, 0F, 0Fx, 0Fy, 0FF, 0Ff, 0ff, 0Fx3, 0Fy3,0Fz3, 0Cx, 0Cy, 0Cw, 0Cz, 0Py, 0Sx, 0Sy, 0Sz, 0Cyx2, 0Cxw, 0Cyx, 0Czy, 0Pk, 0Px: (192, 80, 77)
{1 signal} 1, 1Xx, 1Xy, 1Xk, 1Xz, 1Rx, 1Ry, 1Rk, 1Rz, 1Ay, 1Ax, 1Ak, 1Az, 1Nx, 1Ny, 1f, 1F, 1Fx, 1Fy, 1FF, 1Ff, 1ff, 1Fx3, 1Fy3, 1Fz3, 1Cx, 1Cy, 1Cw, 1Cz, 1Py, 1Sx, 1Sy, 1Sz, 1Cyx, 1Cxw, 1Czy, 1Cyx2, 1Pk, 1Px: (255, 255, 0)
{Reset Signal} RRXz, RXz, RRRz, RRz, RRAz, RAz, RCw, RCz, RCcw, RCcz: (255, 102, 0)
{Holding Input} HXx, HXy, HRx, HRy, HAx, HAy, HCx, HCy: (200, 200, 100)
{Blank Wire} B: (191, 191, 191)
{Inert State} I: (255, 255, 255)

### GATES
{Sync Gate} BSx, BSy: (251, 174, 210)
{XOR Gate} BXx, BXy, BXz: (79, 29, 189)
{OR Gate} BRx, BRy, BRz: (79, 129, 189)
{AND Gate} BAx, BAy, BAz: (155, 187, 89)
{NOT Gate} BNx, BNy: (247, 150, 70)
{Repeater Gate} BPx, BPy: (200, 200, 200)

### WIRE UTILITIES
{Fan-Out} BF, BF3, BFx, BFy, BFx3, BFy3, BFz3: (0, 0, 0)
{Wire Cross} BC, Bx, BCw, BCz, BCx, BCy: (127, 127, 127)
!END_COLORMAP

!START_INIT_STATE
0,B,BRx,BRz,B,B,B,BNx,BNy,B,BF,BFx,B,B,B,I,I,I,I
I,I,I,BRy,I,I,I,I,I,I,BFy,I,I,I,B,I,I,I,I
0,B,B,B,I,I,I,I,I,I,B,I,I,I,B,I,I,I,I
I,I,I,I,I,I,I,I,I,I,BCx,I,I,I,BAx,I,I,I,I
I,I,I,I,I,B,BAx,BAz,B,BCy,BC,BCz,B,BAy,BAz,B,BNx,I,I
I,I,I,B,B,B,I,BAy,I,I,BCw,I,I,I,I,I,BNy,B,B
I,I,I,BCz,I,I,I,B,I,I,B,B,I,I,I,I,I,I,B
1,B,BCx,BC,BCw,B,I,BFx3,I,I,I,B,B,B,B,B,I,I,B
I,I,I,BCy,I,B,B,BF3,BFz3,B,I,I,I,I,I,BRx,I,I,BAx
I,I,B,B,I,I,I,BFy3,I,B,B,BAx,BAz,B,BRy,BRz,B,BAy,BAz
I,I,B,I,I,I,I,B,B,I,I,I,BAy,I,I,I,I,I,B
I,I,BFx3,I,I,I,I,I,BCx,I,BNx,BNy,B,I,I,I,I,I,BNx
1,B,BF3,BFz3,B,B,B,BCy,BC,BCz,B,I,I,I,I,I,I,I,BNy
I,I,BFy3,I,I,I,I,I,BCw,I,I,I,I,I,I,I,I,I,B
I,I,B,I,I,I,I,I,B,I,I,I,I,I,I,I,I,I,I
I,I,B,I,I,I,I,I,BRy,I,I,I,I,I,I,I,I,I,I
I,I,B,B,B,B,B,BRx,BRz,B,I,I,I,I,I,I,I,I,I
!END_INIT_STATE
